A flip-chip semiconductor package with a lead frame is a combination of the lead frame serving as a chip carrier and a flip-chip structure in which a semiconductor chip is mounted on the lead frame in a flip-chip manner. Such semiconductor package comprises: the lead frame having a plurality of leads, or having a plurality of leads and a die pad; at least one chip, which is mounted and electrically connected to the leads via a plurality of solder bumps formed on an active surface of the chip, or which is mounted on the die pad and electrically connected to the leads via a plurality of solder bumps formed on the active surface of the chip; and an encapsulation body for encapsulating the lead frame, the chip and the solder bumps. This packaging technology provides an advantage that the solder bumps are self-aligned and can be completely bonded to the leads in a single process, which thereby is relatively more time- and labor-effective, unlike a conventional wiring method by which a plurality of bonding wires for the electrical connection between chip and leads need to be formed one by one.
Since the solder bumps are usually made of tin (Sn) 63/lead (Pb) 37 alloy, and the lead frame is made of a solderable metal such as copper, during a reflow process for soldering the solder bumps to the leads, the solder bumps under a particular high temperature would melt and collapse to form eutectic, thus resulting in an intermetallic compound between the solder bumps and the leads, and which is customarily referred to as a wetting step. Since the copper-made leads have good wettability, the solder bumps bonded to predetermined positions on the leads may keep collapsing and diffuse to other areas on the leads. This over-collapsing effect not only causes bridging between adjacent solder bumps and electrical failure, but also degrades the quality of mounting the chip on the lead frame and adversely affects the performance of subsequent fabrication processes due to serious deformation of the solder bumps.
In accordance with the above drawbacks, there are developed several methods of performing a soldering-proof treatment for a lead frame. One is disclosed in Taiwanese Patent No. 540123. As shown in FIG. 5, a recess 12 is formed at a bonding area on each lead 10 of a lead frame 1, and a protruded block member 13 is provided beside the recess 12, wherein the bonding area is a predetermined position where a solder bump 11 is subsequently implanted. The block member 13 can be a polyimide tape, a solder mask, or a suitable resin material. When a chip 14 formed with solder bumps 11 thereon is to be mounted on the leads 10, the solder bumps 11 are reflowed to the recesses 12 at the bonding areas on the leads 10. The blocks 13 would prevent over collapsing of the solder bumps 11, and the recesses 12 increase a contact area for wetting, such that the solder bumps would only collapse within the bonding areas but not over collapse or diffuse to other areas on the leads 10.
Another soldering-proof treatment for a lead frame is disclosed in U.S. Pat. No. 6,661,087. As shown in FIG. 6, a lead frame 1′ having a die pad 15 and a plurality of leads 10 is used, wherein the die pad 15 is raised in elevation by a conventional stamping technique to be higher than the leads 10, forming a predetermined height difference between the die pad 15 and the leads 10, and this height difference does not exceed a height of solder bumps 11 that are used for electrically connecting a chip 14 to the leads 10. When the solder bumps 11 formed on the chip 14 are to be bonded to the leads 10, during a reflow process heated to a particular temperature, the solder bumps 11 start collapsing, and the chip 14 is moved downwardly by gravity attraction due to its weight until reaching the die pad 15. At this time, the chip 14 is blocked by the die pad 15 from further movement and stops, making the solder bumps 11 stop collapsing to remain at a fixed height (which is equal to the height difference between the die pad 15 and the leads 10). This thereby can prevent over-collapsing of the solder bumps 11.
However, the methods shown in FIGS. 5 and 6 need to form recesses and block members on the leads of the lead frame (FIG. 5) and to raise the die pad of the lead frame and form a height difference between the die pad and the leads (FIG. 6). Such structured lead frames require complex fabrication processes and make the fabrication cost increased. Moreover, in FIG. 6, the central area of the chip is attached to the die pad. In case bond pads on the chip for mounting solder bumps are provided at or close to the central area, such chip is not suitably subject to the method of FIG. 6.
Therefore, the problem to be solved here is to provide a flip-chip semiconductor package with a lead frame, which can be fabricated by simplified processes without greatly increasing the cost, and also can prevent solder bumps for electrically connecting a chip to leads from over-collapsing, as well as assure the reliability of the fabricated package.